1. Field of the Invention
The present invention relates to an automatic lay-out method using a cell group constituted of a minimum cell (hereinafter called core cell) in which a transistor and/or a logic gate are arranged and a passage region cell (hereinafter called wiring cell) through which a power-supply line and an inter-core cell electrical connection signal (hereinafter called inter-cell signal) line pass.
2. Description of the Related Art
Lay-out design of a semiconductor integrated circuit is always accompanied by a requirement for as much reduction in area as possible. In automatic lay-out design by use of a core cell and a wiring cell, a key to reduction in area is how to select a wiring cell containing any given number of grids.
In a lay-out method disclosed in Japanese Patent Application Laid-Open No. 2001-7209, a primitive cell group is used to set two or more of arbitrary numbers of grids to perform a lay-out operation as many times as this set number, to provide a design having a minimum area as final data.
In the case of this lay-out method, however, there coexist in each design a region where an inter-cell signal line passes through densely and that where it passes through sparsely, so that this region where the signal line passes through sparsely may in some cases have an excessive set number of grids therein and so has not been utilized effectively for the purpose of area reduction. This is because by this method only one of various numbers of grids can be set for each design.
Such an area reduction tool is available as to develop a cell construction in a design to reduce a spacing between inter-cell signal lines according to design rules. This processing is performed after converting data obtained as a result of automatic lay-out into data having a different format and cannot be re-converted into the data of an automatic lay-out format.
Therefore, when a design needs to be changed, data obtained as a result of reduction cannot be re-utilized. Furthermore, a cell construction is eliminated, thus increasing time for design check and a required capacity of a processor.
It is an object of the present invention to provide a semiconductor integrated circuit automatic lay-out method using a cell group constituted of a core cell in which a transistor and/or a logic gate are arranged and a wiring cell through which a power line and an inter-cell signal line between the core cells pass, comprising the steps of using the core cell and the wiring cell in an environment in which the number of grids for the inter-cell signal line is arbitrarily set in initial setting for automatic lay-out; detecting the number of the inter-cell signal lines which pass through the wiring cell of data obtained through cell arrangement and wiring processing; comparing the detected number of the inter-cell signal lines to the number of the initially set grids; and if the number of the grids is excessive or insufficient, replacing an initially set wiring cell with a wiring cell having the detected number of inter-cell signal lines.